This invention relates in general to electrical devices, and more particularly, to a layout for a ball grid array device.
Because every solder ball pad on a surface mounted ball grid array (BGA) device needs an interconnection via, present layout techniques require routing around or using another printed circuit board (PCB) layer to route a signal trace from one side of a BGA package to the other. This present layout technique makes interconnection of BGA packages and surrounding components difficult.
Referring to FIG. 1, there is shown a BGA package 100 having a solder ball pad and interconnection via layout in accordance with the prior art. Multi-layer PCB""s such as BGA package 100 are designed with horizontal (X-axis) and vertical (Y-axis) layers. Pads 102, the top pads, are designed to receive the solder balls for the BGA package, while interconnection vias 104 interconnect a specific solder ball pad 102 through the different PCB layers in the BGA package 100.
As shown in FIG. 1, the interconnection vias 104 are all set at the same 45xc2x0 angle to the solder ball pads 102. FIGS. 2-4 show some of the inner PCB layers 200, 300, 400 and highlight the typical interconnect traces used with the prior art BGA package 100. As shown, using the same 45xc2x0 angle for all of the interconnection vias 104 does not leave much room in the inner layers 200, 300 and 400 for routing traces. A need thus exists for a BGA package layout that helps improve the ability to route traces and may also help decrease the BGA board area and/or number of layers needed for the layout.